1. Field of the Invention
The present invention relates to a polishing method, a semiconductor device fabrication method, and a semiconductor fabrication apparatus and, more particularly, to CMP (Chemical Mechanical Polishing).
2. Description of the Related Art
Semiconductor devices such as ICs and LSIs are typically fabricated through the following steps: an integrated circuit designing step of designing integrated circuits; a photomask formation step of forming a photomask used in a lithography step; a wafer manufacturing step of manufacturing wafers having a predetermined thickness from a single-crystal ingot; a wafer processing step of forming a plurality of integrated circuits on each wafer; a dicing step of dicing each of the integrated circuits formed on the wafer into the shape of a semiconductor chip; an assembly step of packaging the diced semiconductor chips; and a testing step of testing the packaged semiconductor chips. Of these steps, the wafer processing step is most important. The wafer processing step is further subdivided into a thin film deposition step of depositing a thin film, a lithography step of exposing/developing a photoresist, an etching step of etching a wafer or the deposited thin film, and an ion implantation step of implanting an impurity ion into the wafer or the deposited thin film. These steps are done by using semiconductor fabrication apparatuses dedicated to the respective steps.
The techniques used in the etching step are roughly classified into two categories.
One is selective etching in which the target surface is masked using a photoresist and only selected portions are etched. This etching is used in the patterning of interconnections and the formation of contact holes.
The other is etch back by which a whole wafer is evenly etched. This etch back is performed to planarize the wafer surface roughened by interconnections or planarize the wafer surface after trenches or recesses are buried with a thin film. As a method of etch back, a method of performing RIE (Reactive Ion Etching) on the wafer surface after recesses on the wafer surface are buried with a photoresist is used most often (this method will be referred to as etch back-RIE hereinafter). Unfortunately, this etch back-RIE has some disadvantages that the method requires a step of coating the target surface with a photoresist, damages easily remain on the wafer surface after etch back, a dangerous etching gas is used in an RIE apparatus, and the global planarization of an entire wafer is rather low due to variations of the etching rate on the wafer surface.
In consideration of these drawbacks, CMP (Chemical Mechanical Polishing) is recently beginning to be studied in place of etch back-RIE.
In CMP, the surface to be polished of a wafer is pressed against a polishing pad adhered to a polishing disc, and the wafer and the polishing disc are rotated while a polishing agent is supplied to the polishing pad, thereby polishing the surface to be polished. The polishing agent used in CMP is a liquid prepared by dispersing polishing particles which mechanically polish the surface to be polished in a polishing solution which chemically etches the surface. This liquid polishing agent has a function of setting the surface to be polished in an active state in which the surface is readily chemically polished, thereby assisting the mechanical polishing by the polishing particles. This liquid polishing agent is called a slurry.
CMP can alleviate some problems of etch back-RIE. However, although CMP can achieve high global planarization, the local planarization obtained by CMP is found to be low in fine portions of a semiconductor device structure. When the wafer surface planarized by using CMP is observed, fine micron-order dish-like recesses called "dishing" are found in fine portions of a semiconductor device structure, particularly in portions made from different substances on the wafer surface.
A typical condition in which "dishing" occurs will be described below with reference to FIGS. 1A to 1D.
FIGS. 1A to 1D are sectional views showing trench isolation steps in order.
FIG. 1A shows the state in which trenches 5 are formed in a silicon substrate 1. A polishing stopper film 2 is formed on the surface of the silicon substrate 1 except the portions in which the trenches 5 are formed. This stopper film 2 is a nitride film (Si.sub.3 N.sub.4).
Subsequently, as shown in FIG. 1B, silicon dioxide (SiO.sub.2) is deposited inside the trenches 5 and on the stopper film 2, forming an oxide film 6. The trenches 5 are buried with the oxide film 6.
In FIG. 1C, CMP is performed for the oxide film 6. As a consequence, the surface of the oxide film 6 dishes to form "dishing" 7.
In FIG. 1D, the stopper film 2 is removed.
In trench isolation in which the "dishing" 7 is formed as shown in FIGS. 1C and 1D, a conductive thin film may remain in the "dishing" 7. If a conductive thin film remains in the "dishing" 7, this film can bring about defective insulation in the future. This influences the reliability of the semiconductor device.